Product Summary

The EPM7064STC100-10N is a programmable logic device. The EPM7064STC100-10N high-density, high-performance PLDs is based on Alteras second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM7064STC100-10N provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.

Parametrics

EPM7064STC100-10N absolute maximum ratings: (1)VCC Supply voltage With respect to ground: –2.0 to 7.0 V; (2)VI DC input voltage: –2.0 to 7.0 V; (3)IOUT DC output current, per pin: –25 to 25 mA; (4)TSTG Storage temperature No bias: –65 to 150℃; (5)TAMB Ambient temperature Under bias: –65 to 135℃; (6)TJ Junction temperature Ceramic packages, under bias: 150℃; (7)PQFP and RQFP packages, under bias: 135℃.

Features

EPM7064STC100-10N features: (1)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (2)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (3)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates; (4)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (5)PCI-compliant devices available.

Diagrams

EPM7064STC100-10N Block Diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)		 Quantity
EPM7064STC100-10N
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