XC2S50-5PQG208C

Field-Programmable Gate Array, QFP208, -0.5 to 3.0V, Efficient multiplier support, Fully PCI compliant

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Price:: US $4.70~4.80 / piece [Get Latest Price]

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	US $4.70~4.80

PartNumber:: XC2S50-5PQG208C

Brand:: Xilinx, Inc - Xilinx | Pack: QFP | D/C: 09+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-12-06

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Part Number:XC2S50-5PQG208C
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Product Summary

The XC2S50-5PQG208C is a member of Spartan-II Field-Programmable Gate Array family. It is a superior alternative to mask-programmed ASICs. The device avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, the XC2S50-5PQG208C programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs). Features include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I/O standards, and four DLLs.

Parametrics

XC2S50-5PQG208C absolute maximum ratings: (1)VCCINT Supply voltage relative to GND: min=–0.5V, max=3.0 V; (2)VCCO Supply voltage relative to GND: min=–0.5V, max=4.0 V; (3)VREF Input reference voltage: min=–0.5V, max=3.6 V; (4)VIN Input voltage relative to GND 5V tolerant I/O: min=–0.5V, max=5.5 V; No 5V tolerance: min=–0.5V, max=VCCO+0.5 V; (5)VTS Voltage applied to 3-state output 5V tolerant I/O: min=–0.5V, max=5.5 V; No 5V tolerance: min=–0.5V, max=VCCO+0.5 V; (6)TSTG Storage temperature (ambient): min=–65℃, max=+150 ℃; (7)TJ Junction temperature: max=+125 ℃.

Features

XC2S50-5PQG208C features: (1)Fully PCI compliant; (2)Low-power segmented routing architecture; (3)Full readback ability for verification/observability; (4)Dedicated carry logic for high-speed arithmetic; (5)Efficient multiplier support; (6)Cascade chain for wide-input functions; (7)Abundant registers/latches with enable, set, reset; (8)Four dedicated DLLs for advanced clock control; (9)Four primary low-skew global clock distribution nets; (10)IEEE 1149.1 compatible boundary scan logic.