XC3S250E-4CPG132C

Field-Programmable Gate Array, BGA132, low cost, high-performance logic solution, 3.5V

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Price:: US $11.00~11.50 / piece [Get Latest Price]

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	US $11.00~11.50

PartNumber:: XC3S250E-4CPG132C

Brand:: Xilinx, Inc - Xilinx | Pack: BGA | D/C: 09+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-10-31

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Part Number:XC3S250E-4CPG132C
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Product Summary

The XC3S250E-4CPG132C is a Field-Programmable Gate Array. It is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The XC3S250E-4CPG132C builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. The XC3S250E-4CPG132C is a superior alternative to mask programmed ASICs.

Parametrics

XC3S250E-4CPG132C absolute maximum ratings: (1)Internal supply voltage:-0.5V to 1.32V; (2)Auxiliary supply voltage:-0.5V to 3.00V; (3)Output driver supply voltage:-0.5V to 3.75V; (4)Input reference voltage:-0.5V to VCCO+0.5V; (5)Voltage applied to all User I/O pins and Dual-Purpose pins:-0.5V to VCCO+0.5V; (6)Voltage applied to all Dedicated pins:-0.5V to VCCAUX+0.5V; (7)Electrostatic Discharge Voltage:-2000V to +2000V; (8)Junction temperature:125℃; (9)Storage temperature:-65℃ to 150℃.

Features

XC3S250E-4CPG132C features: (1)Very low cost, high-performance logic solution for high-volume, consumer-oriented applications; (2)Proven advanced 90-nanometer process technology; (3)Up to 376 I/O pins or 156 differential signal pairs; (4)LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards; (5)True LVDS, RSDS, mini-LVDS differential I/O; (6)3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling; (7)Enhanced Double Data Rate (DDR) support; (8)Densities up to 33,192 logic cells, including optional shift register or distributed RAM support; (9)Efficient wide multiplexers, wide logic; (10)Fast look-ahead carry logic; (11)Enhanced 18 x 18 multipliers with optional pipeline; (12)IEEE 1149.1/1532 JTAG programming/debug port; (13)Up to 648 Kbits of fast block RAM ; (14)Up to 231 Kbits of efficient distributed RAM; (15)Clock skew elimination (delay locked loop); (16)Frequency synthesis, multiplication, division; (17)High-resolution phase shifting; (18)Wide frequency range (5 MHz to over 300 MHz); (19)Low-cost, space-saving SPI serial Flash PROM; (20)x8 or x8/x16 parallel NOR Flash PROM; (21)Low-cost Xilinx Platform Flash with JTAG.